Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures

ABSTRACT

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to integrated circuit manufacturing and, more particularly, to a substantially planarized interconnect topography and method for making substantially planarized electrically conductive features such as wide interconnect structures by fabricating the electrically conductive features around a plurality of posts.

[0003] 2. Description of the Related Art

[0004] Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then patterned across the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.

[0005] As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers may arise from incomplete etching over severe steps. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. The presence of such elevational disparities therefore makes it difficult to print high-resolution features.

[0006] Techniques involving chemical and mechanical abrasion (e.g., chemical-mechanical polishing) to planarize or remove the surface irregularities have grown in popularity. As shown in FIG. 1, a typical chemical-mechanical polishing (“CMP”) process involves placing a semiconductor wafer 12 face-down on a polishing pad 14 which lies on or is attached to a rotatable table or platen 16. A popular polishing pad medium includes polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad 14 and semiconductor wafer 12 may be rotated while a carrier 10 holding wafer 12 applies a downward force F upon polishing pad 14. An abrasive, fluid-based chemical suspension, often referred to as a “slurry”, may be deposited from a conduit 18 positioned above pad 14 onto the surface of polishing pad 14. The slurry may fill the space between pad 14 and the surface of wafer 12. The polishing process may involve a chemical in the slurry reacting with the surface material being polished. The rotational movement of polishing pad 14 relative to wafer 12 preferably causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer 12. The pad 14 itself may also physically remove some material from the surface of the wafer 12. The abrasive slurry particles are typically composed of silica, alumina, or ceria.

[0007] CMP is commonly used to form a planarized level of an integrated circuit containing interconnect laterally spaced from each other in what is generally referred to as the “damascene” process. Laterally spaced trenches are first etched in an interlevel dielectric configured upon a semiconductor topography comprising electrically conductive features. A conductive material is then deposited into the trenches and on the interlevel dielectric between trenches to a level spaced above the upper surface of the interlevel dielectric. CMP is applied to the surface of the conductive material to remove that surface to a level substantially commensurate with that of the upper surface of the interlevel dielectric. In this manner, interconnect that are isolated from each other by the interlevel dielectric are formed exclusively in the trenches. CMP can planarize only localized regions of the interconnect surface such that all interconnect traces have a coplanar upper surface, provided certain conditions are met. The localized area must contain trenches that are consistently and closely spaced from each other. Moreover, the trenches must be relatively narrow in lateral dimension. If those rather restrictive requirements are not met, then thicknesses of a given interconnect layer can vary to such a degree that local regions of interconnect may suffer severe current-carrying limitations.

[0008] In particular, planarization may become quite difficult in a region where there is a relatively large distance between a series of relatively narrow interconnect, or if there is a relatively wide interconnect such as that found in, for example, a bond pad or a wide conductive line, such as a bus. FIGS. 2-5 illustrate a typical damascene process and the localized thinning or “dishing” problem experienced by conventional metal CMP processes when a relatively wide interconnect is planarized.

[0009]FIG. 2 depicts a partial top view of a bond pad 22, possibly up to or exceeding 100 μm per side, formed in an interlevel dielectric 20 according to a conventional process. FIG. 3 shows a partial cross-sectional view of the semiconductor topography including the bond pad along line A. A relatively wide trench 24 is formed in interlevel dielectric 20 using well-known lithography and etch techniques. FIG. 4 illustrates a conductive material 28, e.g., a metal, such as aluminum, tungsten, tantalum, or titanium, deposited across the topography to a level spaced above upper surface 26. Due to the conformal nature of the sputter or CVD process used to apply the conductive material, the conductive material takes on an upper surface topography including a region 30 having a single wide valley area spaced above the wide trench 24 and a substantially flat region 32 spaced above smooth upper surface 26. Conductive material 28 is then polished, as shown in FIG. 5, using CMP to remove conductive material 28 from the upper surface of interlevel dielectric 20. As a result of CMP, a relatively wide interconnect 34 is formed exclusively in wide trench 24. As shown in FIG. 5, the wide interconnect 34 may subsequently function as a bond pad. A similar process may be used to form other wide interconnects, such as buses or other wide conductive lines.

[0010] Unfortunately, the topological surface of the interconnect level is not absent of elevational disparity. That is, the upper surface of interconnect 34 includes a recessed area 36 that extends below a substantially planar upper surface 38 of interlevel dielectric 20. Recessed area 36 may result from a phenomenon known as the “dishing” effect. Dishing naturally results from the polishing pad flexing or conforming to the surface being polished. If the surface being polished is initially bowed or arcuate (i.e., is not planar), the polishing pad will take on the shape of the non-planar regions causing further dishing of the surface being polished. The CMP slurry initiates the polishing process by chemically reacting with the surface material in both elevated and recessed areas. Because of the deformation of the CMP pad, the reacted surface material in recessed areas may be physically stripped in addition to the reacted surface material in elevated areas. As such, a surface having fluctuations in elevation may continue to have some elevational disparity even after it has been subjected to CMP. The dishing effect is particularly a problem when forming a relatively wide interconnect between regions of a dielectric that is substantially more dense than the metal. While the dielectric is hard enough to support the overlying regions of the CMP pad, the metal is not, and thus allows significant flexing of the pad. Such flexing of the CMP pad may cause the surface of the metal interconnect to become recessed relative to adjacent regions of the dielectric.

[0011] It would therefore be desirable to develop a polishing process which can achieve global planarization across the entire topological surface of an interconnect level. Global planarization requires that the polish rate be uniform in all elevated areas of the topography. Such uniformity of the polish rate is particularly needed when polishing a topography having a relatively wide interconnect, a wide interconnect interspersed with other wide interconnects, or a wide interconnect interspersed with densely spaced or sparsely spaced narrow (or “small”) interconnects. The desired polishing process must avoid problems typically arising during CMP of varying metal substrate area, such as metal dishing.

SUMMARY OF THE INVENTION

[0012] The problems outlined above are in large part solved by an embodiment of the present invention in which a substantially planar semiconductor topography is fabricated by forming a plurality of posts in a dielectric layer in a region defined by a relatively wide interconnect. The dielectric layer may include a material having a relatively low dielectric constant such as a glass- or silicate-based dielectric, preferably silicon dioxide.

[0013] According to an embodiment, trenches are first etched in the dielectric layer to form a plurality of posts surrounded by the trenches. The widths, lengths, and depths of the trenches and the widths of the posts may vary according to design preferences and criteria. In an embodiment in which a bond pad is to be formed, both the trenches and the posts may have widths of about 10 μm. In an alternative embodiment, the trenches may have a width of about 9 μm and the posts may have a width of about 1 μm. The overall length (lateral dimension) of the etched area is preferably between about 75 μm and about 100 μm. The depth of the trenches is preferably greater than about 0.2 μm. According to an embodiment in which a wide conductive line such as, e.g., a power or ground conductor within a bus is to be formed, the conductive line may have a width of at least about 5 μm and the posts may have a width of at least about 1 μm. The depth of the trenches is preferably greater than about 0.2 μm.

[0014] The trenches are filled with a conductive material, e.g., a metal or an alloy of a metal such as aluminum, copper, tungsten, molybdenum, tantalum, or titanium. The conductive material is preferably deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with the level of the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches and the posts is substantially uniform. The posts preferably serve to improve the planarization of the conductive material surrounding them.

[0015] In one embodiment, the conductive material may be polished using well-known CMP. That is, the front side of the semiconductor topography may be forced against a CMP polishing pad while the polishing pad and the topography are rotated relative to each other. A CMP slurry entrained with abrasive particles, e.g., ceria, silica, or alumina, may be dispensed upon the polishing pad surface to aid in the removal of the conductive material. In an alternate embodiment, a “fixed-abrasive” technique may be used to polish the conductive material. The fixed-abrasive technique involves placing a liquid that is substantially free of particulate matter between the surface of the conductive material and an abrasive polishing surface of a polishing pad. The fixed abrasive technique avoids liquids that contain chemical constituents that could react with the topography. The abrasive polishing surface is moved relative to the semiconductor topography so as to polish the conductive material. The liquid applied to the polishing surface preferably comprises deionized water, however, other liquids which have a near-neutral pH value may alternatively be directed onto the fixed abrasive polishing surface. The pH that is chosen for the polishing process is one suitable for the conductive material and the polishing pad. The polishing surface may include a polymer-based matrix entrained with particles selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide.

[0016] The abrasive polishing surface preferably belongs to a polishing pad which is substantially resistant to deformation even when placed across an elevationally recessed region of relatively large lateral dimension (e.g., over 200 μm lateral dimension). Therefore, the pad is preferably relatively non-conformal to the underlying surface and thus does not come in contact with elevationally recessed regions of the conductive material. It is believed that particles dispersed throughout the abrasive polishing surface in combination with the polishing liquid interact chemically and physically with elevated regions of the conductive material to remove those regions. However, the liquid alone may be incapable of removing the conductive material in elevationally recessed regions. As such, elevationally raised regions of the conductive material may be removed at a substantially faster rate than elevationally recessed regions. The polish rate preferably slows down significantly as the topological surface of the interconnect level approaches planarity.

[0017] Whatever polishing technique is applied to the conductive material, the presence of the posts within the conductive material preferably provides for global planarization of the topography employing the posts. It is theorized that the dielectric material of the posts, being denser than the conductive material, causes the polishing pad to remain substantially flat when pressure is applied thereto. That is, the surface area of the dielectric protrusions within the conductive material is not sufficient to withstand the force of the polishing pad, and thus does not cause the pad to flex. Therefore, dishing of the conductive material in the large area metal-filled trenches (e.g., bond pads greater than about 75 μm per side or interconnects greater than about 5 μm wide) is less likely to occur as a result of the polishing process.

[0018] The conductive material may continue to be polished more rapidly than the dielectric once the surface of the conductive material has been removed to the same elevational plane as the dielectric. The dielectric protrusions within the conductive material may thus become elevated above the conductive material. Consequently, the entire topological surface of the bond pad may have surface disparities, causing the polish rate of the elevated dielectric protrusions to become greater than that of the recessed conductive material. As the polishing process continues, the dielectric protrusions are again made substantially coplanar with the conductive material. This cycle may be repeated until it is desirable to stop the polishing process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

[0020]FIG. 1 depicts a side plan view of an apparatus that may be used to chemical-mechanical polish a semiconductor topography;

[0021]FIG. 2 depicts a partial top view of a conventional semiconductor topography including a bond pad;

[0022]FIG. 3 depicts a partial cross-sectional view of the semiconductor topography, wherein a relatively wide trench is formed within an interlevel dielectric;

[0023]FIG. 4 depicts a partial cross-sectional view of the semiconductor topography, wherein a conductive material is deposited into the trench to a level spaced above an upper surface of the interlevel dielectric;

[0024]FIG. 5 depicts a partial cross-sectional view of the semiconductor topography, wherein the surface of the conductive material is removed from the upper surface of the interlevel dielectric using a conventional CMP technique, thereby forming a topological surface having elevational disparities;

[0025]FIG. 6 depicts a partial top view of a semiconductor topography according to an embodiment of the present invention, including a bond pad having a plurality of dielectric posts surrounded by a conductive material;

[0026]FIG. 7 depicts a partial perspective view of the semiconductor topography, wherein a photoresist layer is formed above a dielectric layer;

[0027]FIG. 8 depicts a partial perspective view of the semiconductor topography, wherein the photoresist is lithographically patterned;

[0028]FIG. 9 depicts a partial perspective view of the semiconductor topography, wherein the dielectric layer is selectively etched to form a plurality of dielectric posts surrounded by trenches;

[0029]FIG. 10 depicts a partial perspective view of the semiconductor topography, wherein the photoresist is removed from upon the dielectric layer;

[0030]FIG. 11 depicts a partial perspective view of the semiconductor topography, wherein a conductive material is deposited into the trenches to a level spaced above the upper surfaces of the dielectric layer and the posts;

[0031]FIG. 12 depicts a partial perspective view of the semiconductor topography, wherein the surface of the conductive material is removed to a level substantially commensurate with that of the upper surfaces of the dielectric layer and the posts using a planarization process according to an embodiment of the present invention, thereby forming a planarized topological surface;

[0032]FIG. 13 depicts a partial perspective view of the semiconductor topography, wherein a passivation layer is formed according to one embodiment across the upper surfaces of the conductive material, the dielectric layer, and the posts;

[0033]FIG. 14 depicts a partial perspective view of the semiconductor topography, wherein a contact window is formed by removing a portion of the passivation layer from above the conductive material;

[0034]FIG. 15 depicts a partial perspective view of the semiconductor topography, wherein a portion of the posts are removed from within the conductive material exposed by the contact window;

[0035]FIG. 16 depicts a partial top view of a semiconductor topography according to an alternative embodiment of the present invention, including a wide conductive line having a plurality of dielectric posts surrounded by a conductive material;

[0036]FIG. 17 depicts a partial perspective view of the semiconductor topography, wherein a dielectric layer is selectively etched to form a plurality of dielectric posts surrounded by trenches;

[0037]FIG. 18 depicts a partial perspective view of the semiconductor topography, wherein a conductive material is deposited into the trenches and wherein the surface of the conductive material is removed to a level substantially commensurate with that of the upper surfaces of the dielectric layer and the posts using a planarization process according to an embodiment of the present invention, thereby forming a planarized topological surface; and

[0038]FIG. 19 depicts a partial perspective view of the semiconductor topography, wherein an additional dielectric layer is formed upon the semiconductor topography.

[0039] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0040] Turning to FIG. 6, a partial top view of an embodiment of semiconductor topography is presented. Electrically conductive features may be embodied within the topography. As depicted in FIG. 6, semiconductor topography 110 includes a wide interconnect structure 120 formed within a dielectric layer 150. Wide interconnect structure 120 includes bond pad 130 and bus line 140. Bond pad 130 includes conductive portion 170 surrounding a plurality of dielectric posts 160.

[0041]FIG. 7 shows a partial perspective view of the semiconductor topography 110 of FIG. 6 along line B prior to formation of posts 160. According to an embodiment of a method for forming wide interconnect structure 120, a layer of photoresist 152 may be deposited upon dielectric layer 150 and selectively patterned. Dielectric layer 150 may include a dielectric material having a relatively low dielectric constant. Dielectric layer 150 may include, e.g., a glass- or silicate-based material, such as an oxide that has been deposited by chemical-vapor deposition (“CVD”) from either a tetraethyl orthosilicate (“TEOS”) source or a silane source and doped with an impurity, e.g., boron or phosphorus. Dielectric layer 150 may serve as a poly-metal interlevel dielectric (“PMD”) between a doped polycrystalline silicon (“polysilicon” or “poly”) gate layer and an ensuing metal interconnect layer. It is to be understood that the gate layer may include other conductive materials besides polysilicon. Alternatively, dielectric 150 may form an inter-metal interlevel dielectric (“IMD”) between an underlying metal interconnect layer and an ensuing overlying metal interconnect layer.

[0042] Photoresist 152 may be lithographically patterned as shown in FIG. 8 to expose select portions 156 of the dielectric 150. The patterning of the photoresist may leave retained photoresist portions 154 having a width S upon dielectric layer 150 and separated from each other by a distance W. For example, in an embodiment, S may be about 10 μm and W may be about 10 μm. According to an alternative embodiment, S may be about 1 μm and W may be about 9 μm. Photoresist 152 may be removed from dielectric layer 150 over an area having a total width L (see FIG. 6) in which bond pad 130 is to be formed. In an embodiment, L may be between about 75 μm and about 125 μm.

[0043] The select portions 156 of dielectric layer 150 not covered by the patterned photoresist 154 may then be etched using an etch technique such as a CF₄ plasma etch, as shown in FIG. 9, followed by removal of the patterned photoresist, as shown in FIG. 10. The etching preferably forms trenches 158 having a depth D and a width W within dielectric layer 150. According to an exemplary embodiment, depth D may be between about 0.2 μm and about 1.0 μm. Portions of dielectric layer 150 masked by patterned photoresist 154 may be retained and may form posts 160 of width S. Following the etching, photoresist 154 may be removed from upon dielectric layer 150, as shown in FIG. 10. It should be noted that although bond pad 130 and posts 160 are depicted in FIG. 6 as having a substantially square shape, bond pad 130 and posts 160 may have a variety of topological shapes such as, but not limited to, rectangular, circular, or hexagonal. It should be further noted that although widths S and W are depicted as uniform across the semiconductor topography, trenches and posts of varying dimensions may be formed.

[0044] Turning now to FIG. 11, a layer of conductive material may be deposited across the semiconductor topography, preferably to a level spaced above the uppermost horizontal surface of dielectric layer 150 and posts 160. Conductive material 162 may include a metal such as aluminum, copper, tungsten, molybdenum, tantalum, titanium, or alloys thereof. Such a metal may be sputter deposited from a metal target or MOCVD (i.e., metal organic CVD) deposited from a metal organic source. The as-deposited conductive material 162 may have an elevationally disparate surface, with valley areas 164 directly above trenches 158 and hill areas 166 directly above posts 160 between the trenches.

[0045] Turning now to FIG. 12, conductive material 162 may be polished to a level substantially coplanar with the uppermost surface of dielectric layer 150 and posts 160. As a result of polishing conductive material 162, conductive portion 170 of bond pad 130 is formed in trenches 158. Placing posts 160 between the series of trenches 158 affords global planarization of the topological surface. That is, the polish rate is substantially uniform across the entire topological surface. Also, the polish rate of elevationally raised regions is greater than that of elevationally recessed regions. Further, a surface having elevational disparity is polished at a faster rate than a substantially flat surface.

[0046] It is believed that the presence of posts 160 helps prevent the polishing pad from deforming about the length of the pad when the pad is subjected to normal pressure, as may occur when polishing a relatively wide trench. Further, it is postulated that posts 160 ensure that elevational fluctuations are present in different regions of the topological surface at the same time. That is, no particular region of the topological surface becomes substantially planarized before other regions and thereby causes fluctuations in the polish rate across the surface. Thus, the polish rate does not slow down until the entire topological surface is substantially free of elevational disparity.

[0047] Following the formation of bond pad 130, a passivation layer may be formed upon the semiconductor topography, as shown in FIG. 13. Passivation layer 180 may seal out moisture and contaminants and protect the underlying structures from scratches. In an embodiment, passivation layer 180 may include a dielectric material. The dielectric material may include, for example, a CVD phosphosilicate glass or a plasma-enhanced silicon nitride. An opening 182 may be formed in passivation layer 180 to expose portions of bond pad 130, as shown in FIG. 14. Wires may be connected to metal 170 of bond pad 130 and to a chip package (not shown) to establish connections from the chip to the package leads.

[0048] Opening 182 maybe formed using a photolithography process similar to the process described for forming posts 160 and trenches 158 (FIGS. 8-9). In an embodiment, the etchant used to remove patterned portions of passivation layer 180 may also remove posts 160 from within conductive portion 170, as shown in FIG. 15. As such, when a wire is connected to bond pad 130, the connection preferably will be only to conductive portion 170 and not to a dielectric portion such as posts 160.

[0049]FIG. 16 depicts a partial top view of an alternative embodiment of a semiconductor topography. As depicted in FIG. 16, semiconductor topography 210 includes a wide conductive line 220 formed within a dielectric layer 250. Wide conductive line 220 includes conductive portion 230 surrounding a plurality of dielectric posts 240. FIG. 17 shows a partial perspective view of the semiconductor topography 210 of FIG. 16 along line C. According to an embodiment of a method for forming wide conductive line 220, a layer of photoresist may be deposited upon dielectric layer 250 and selectively patterned as described previously with respect to FIG. 8. Dielectric layer 250 may include a dielectric material having a relatively low dielectric constant and serve as a PMD or IMD as previously described.

[0050] The photoresist may be lithographically patterned and trenches may be formed in dielectric material 250 according to a procedure similar to the method described with respect to FIGS. 8-10. Trenches 258 having a depth D′ and a width W′ are preferably formed within dielectric layer 250. Portions of dielectric layer 250 not removed during trench formation may form posts 240 of width S′. According to an exemplary embodiment, in which the width L′ of the wide conductive line is at least about 5 μm, widths W′ and S′ may be at least about 1 μm and depth D′ may be at least about 0.2 μm. It should be noted that although posts 240 are depicted in FIG. 17 as having a substantially square shape, posts 240 may have a variety of shapes such as, but not limited to, rectangular, circular, or hexagonal. It should be further noted that although widths S′ and W′ are depicted as uniform across the semiconductor topography, trenches and posts of varying dimensions may be formed.

[0051] A layer of conductive material (similar to layer 162 shown in FIG. 11) may be deposited across the semiconductor topography, preferably to a level spaced above the uppermost horizontal surface of dielectric layer 250 and posts 240. The conductive material may be polished to a level substantially coplanar with the uppermost surface of dielectric layer 250 and posts 240, as shown in FIG. 18, to form conductive portion 230 of wide conductive line 220 in trenches 258. Placing posts 240 between the series of trenches 258 affords global planarization of the topological surface as previously described.

[0052] Following the formation of wide conductive line 220, an additional interlevel dielectric 260 may be formed upon the semiconductor topography, as shown in FIG. 19. Additional interlevel dielectric 260 may include, e.g., a glass- or silicate-based material, such as an oxide that has been deposited by chemical-vapor deposition (“CVD”) from either a tetraethyl orthosilicate (“TEOS”) source or a silane source and doped with an impurity, e.g., boron or phosphorus. Dielectric 250 may form an interlevel dielectric between wide conductive line 220 and an ensuing overlying interconnect layer.

[0053] It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a method for forming a substantially planar semiconductor topography by placing a plurality of dielectric posts within a relatively wide interconnect such as a bond pad or wide conductive line. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, electrically conductive features isolated from each other by a dielectric may subsequently be formed upon the planarized semiconductor topography. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. 

What is claimed is:
 1. A method for forming a semiconductor topography having a substantially planar electrically conductive feature, comprising: forming a plurality of trenches within a region of a dielectric layer to form from said dielectric layer a plurality of posts surrounded by said trenches; filling said trenches with a conductive material; and planarizing upper surfaces of said conductive material to an elevational level commensurate with upper surfaces of said dielectric layer.
 2. The method as recited in claim 1 wherein forming said plurality of trenches comprises: depositing a layer of photoresist upon said dielectric layer; patterning said photoresist; removing said photoresist from first regions of said dielectric layer where said trenches are to be formed while retaining said photoresist upon second regions of said dielectric layer from which said posts are to be formed; and removing a portion of said dielectric layer from said first regions to form said trenches while retaining said dielectric layer in said second regions.
 3. The method as recited in claim 1 wherein filling said trenches with a conductive material comprises depositing a metal.
 4. The method as recited in claim 3 wherein said metal is selected from the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.
 5. The method as recited in claim 1 wherein said planarizing comprises chemical-mechanical polishing.
 6. The method as recited in claim 1, further comprising forming a passivation layer upon said conductive material and said dielectric layer.
 7. The method as recited in claim 6, further comprising removing portions of said passivation layer to form an opening above a portion of said conductive material.
 8. The method as recited in claim 7, further comprising removing said posts subsequent to said forming said passivation layer.
 9. The method as recited in claim 1, further comprising removing said posts subsequent to said filling.
 10. A substantially planar semiconductor topography comprising a conductive interconnect structure formed entirely within a trench and having at least one opening extending entirely through the conductive interconnect structure.
 11. The semiconductor topography as recited in claim 10, further comprising a dielectric material within said at least one opening.
 12. The semiconductor topography as recited in claim 10, further comprising a passivation layer upon said dielectric material.
 13. The semiconductor topography as recited in claim 12 wherein said conductive interconnect structure comprises a bond pad and wherein said passivation layer has an opening formed therein above said conductive material.
 14. The semiconductor topography as recited in claim 10 wherein said conductive interconnect structure comprises a bond pad.
 15. The semiconductor topography as recited in claim 14 wherein said trench comprises a width of about 10 μm, said conductive material comprises a depth of at least about 0.2 μm, said opening comprises a width of about 10 μm, and said bond pad comprises a lateral dimension of between about 75 μm and about 100 μm.
 16. The semiconductor topography as recited in claim 14 wherein said trench comprises a width of about 9 μm, said conductive material comprises a depth of at least about 0.2 μm, said opening comprises a width of about 1 μm, and said bond pad comprises a lateral dimension of between about 75 μm and about 100 μm.
 17. The semiconductor topography as recited in claim 10 wherein said conductive interconnect structure comprises a conductive line.
 18. The semiconductor topography as recited in claim 17 wherein said conductive line comprises a width of at least about 5 μm, said conductive material comprises a depth of at least about 0.2 μm, and said opening comprises a width of about 1 μm.
 19. The semiconductor topography as recited in claim 10 wherein said conductive material comprises a metal.
 20. The semiconductor topography as recited in claim 19 wherein said metal comprises a material selected form the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.
 21. A substantially planar semiconductor topography comprising a conductive interconnect structure formed entirely within a trench and extending laterally between posts rising upward from a base of the trench. 